[CB16] Stephen V. Cole and Jeremy Buhler. MERCATOR (Mapping EnumeRATOR for CUDA) User's Manual. Technical Report WUCSE-2016-003, Dept. of Computer Science and Engineering, Washington University in St. Louis, July 2016. [ bib | pdf ]
[MGC16] John Meier, Christopher Gill, and Roger D. Chamberlain. Combining admission and modulation decisions for wireless embedded systems. In Proc. of 19th IEEE International Symposium on Real-Time Computing (ISORC), May 2016. [ bib | DOI | pdf ]
[CCG+16] Roger D. Chamberlain, Mike Chambers, Darren Greenwalt, Brett Steinbrueck, and Todd Steinbrueck. Layered security and ease of installation for devices on the internet of things. In Proc. of IEEE 1st International Conference on Internet-of-Things Design and Implementation (IoTDI), pages 297--300, April 2016. Presented at 1st International Workshop on Interoperability, Integration, and Interconnection of Internet of Things (I4T), Berlin, Germany. [ bib | pdf ]
[HC15] Michael J. Hall and Roger D. Chamberlain. Using M/G/1 queueing models with vacations to analyze virtualized logic computations. In Proc. of 33rd IEEE International Conference on Computer Design (ICCD), pages 86--93, October 2015. [ bib | pdf ]
[WCC15b] Joseph G. Wingbermuehle, Ron K. Cytron, and Roger D. Chamberlain. Superoptimizing memory subsystems for multiple objectives. In Proc. of 4th International Workshop on On-chip Memory Hierarchies and Interconnects (OMHI), volume 9523 of Lecture Notes in Computer Science, pages 352--363. August 2015. [ bib | pdf ]
[BC15] Jonathan C. Beard and Roger D. Chamberlain. Run time approximation of non-blocking service rates for streaming systems. In Proc. of IEEE 17th International Conference on High Performance Computing and Communications (HPCC), pages 792--797, August 2015. [ bib | pdf ]
[BEC15b] Jonathan C. Beard, Cooper Epstein, and Roger D. Chamberlain. Online automated reliability classification of queueing models for streaming processing using support vector machines. In Proc.of 21st International Conference on Parallel and Distributed Computing (Euro-Par), Lecture Notes in Computer Science, pages 82--93. August 2015. [ bib | pdf ]
[BLC15] Jonathan C. Beard, Peng Li, and Roger D. Chamberlain. RaftLib: A C++ template library for high performance stream parallel processing. In Proc. of 6th International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM), pages 96--105, February 2015. [ bib | pdf ]
[BEC15a] Jonathan C. Beard, Cooper Epstein, and Roger D. Chamberlain. Automated reliability classification of queueing models for streaming computation. In Proc. of 6th ACM/SPEC International Conference on Performance Engineering (ICPE), pages 325--328, February 2015. [ bib | pdf ]
[WCC15a] Joseph G. Wingbermuehle, Ron K. Cytron, and Roger D. Chamberlain. Superoptimized memory subsystems for streaming applications. In Proc. of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pages 126--135, February 2015. [ bib | pdf ]
[LABC14] Peng Li, Kunal Agrawal, Jeremy Buhler, and Roger D. Chamberlain. Orchestrating safe streaming computations with precise control. In Proc. of International Workshop on Extreme Scale Computing Application Enablement - Modeling and Tools (ESCAPE), December 2014. [ bib | pdf ]
[BC14] Jonathan C. Beard and Roger D. Chamberlain. Use of a Levy distribution for modeling best case execution time variation. In A. Horváth and K. Wolter, editors, Computer Performance Engineering, volume 8721 of Lecture Notes in Computer Science, pages 74--88. Springer International Publishing, September 2014. [ bib | DOI | pdf ]
[MAC14a] Lin Ma, K Agrawal, and RD Chamberlain. Analysis of classic algorithms on gpus. In Proc. of the 12th ACM/IEEE Int’l Conf. on High Performance Computing and Simulation (HPCS), pages 65--73, July 2014. [ bib | pdf ]
[HC14b] M.J. Hall and R.D. Chamberlain. Performance modeling of virtualized custom logic computations. In Application-specific Systems, Architectures and Processors (ASAP), 2014 IEEE 25th International Conference on, pages 72--73, June 2014. [ bib | DOI | pdf ]
[MCA14] Lin Ma, R.D. Chamberlain, and K. Agrawal. Performance modeling for highly-threaded many-core gpus. In Application-specific Systems, Architectures and Processors (ASAP), 2014 IEEE 25th International Conference on, pages 84--91, June 2014. [ bib | DOI | pdf ]
[MAC14b] Lin Ma, Kunal Agrawal, and Roger D. Chamberlain. A memory access model for highly-threaded many-core architectures. Future Generation Computer Systems, 30(0):202 -- 215, January 2014. [ bib | DOI ]
[WCC14] Joseph G. Wingbermuehle, Ron K. Cytron, and Roger D. Chamberlain. Superoptimization of memory subsystems. In Proceedings of the 2014 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems, LCTES '14, pages 145--154, New York, NY, USA, 2014. ACM. [ bib | DOI | pdf ]
[HC14a] Michael J Hall and Roger D Chamberlain. Performance modeling of virtualized custom logic computations. pages 89--90. ACM, 2014. [ bib | pdf ]
[MKS+13] John Meier, Benjamin Karaus, Sreeharsha Sistla, Terry Tidwell, Roger D Chamberlain, and Christopher Gill. Assessing the appropriateness of using markov decision processes for rf spectrum management. In Proceedings of the 16th ACM international conference on Modeling, analysis & simulation of wireless and mobile systems, pages 41--48. ACM, November 2013. [ bib | pdf ]
[WCC13a] Joseph G. Wingbermuehle, Ron K. Cytron, and Roger D. Chamberlain. Compiling for power with ScalaPipe. Journal of Systems Architecture, 59(8):615--625, September 2013. [ bib | DOI ]
[PCC13b] Shobana Padmanabhan, Yixin Chen, and Roger D. Chamberlain. Unchaining in design-space optimization of streaming applications. In Proc. of Workshop on Data-Flow Execution Models for Extreme Scale Computing, September 2013. [ bib | pdf ]
[BC13a] Jonathan C. Beard and Roger D. Chamberlain. Analysis of a simple approach to modeling performance for streaming data applications. In Proc. of IEEE Int'l Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pages 345--349, August 2013. [ bib | DOI | pdf | Presentations/MASCOTS_2013.pdf ]
[BC13b] Jonathan C. Beard and Roger D. Chamberlain. Use of simple analytic performance models of streaming data applications deployed on diverse architectures. In Proc. of Int'l Symp. on Performance Analysis of Systems and Software, pages 138--139, April 2013. [ bib | DOI | pdf | Posters/ISPASS_2013.pdf ]
[WCC13b] Joseph G. Wingbermuehle, Ron K. Cytron, and Roger D. Chamberlain. Optimization of application-specific memories. Computer Architecture Letters, April 2013. [ bib | DOI ]
[PCC13a] Shobana Padmanabhan, Yixin Chen, and Roger D. Chamberlain. Decomposition techniques for optimal design-space exploration of streaming applications. In Proc. of 18th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, February 2013. [ bib | DOI | pdf ]
[PCC12] Shobana Padmanabhan, Yixin Chen, and Roger D. Chamberlain. Convexity in non-convex optimizations of streaming applications. In Proc. of 18th IEEE Int'l Conf. on Parallel and Distributed Systems, pages 668--675, December 2012. [ bib | DOI | pdf ]
[MAC12] Lin Ma, Kunal Agrawal, and Roger D. Chamberlain. A memory access model for highly-threaded many-core architectures. In Proc. of IEEE 18th International Conference on Parallel and Distributed Systems, pages 339--347, December 2012. [ bib | DOI | pdf ]
[WCC12] Joseph G. Wingbermuehle, Roger D. Chamberlain, and Ron K. Cytron. ScalaPipe: A streaming application generator. In Proc. Symp. on Application Accelerators in High-Performance Computing, July 2012. [ bib | DOI | pdf ]
[MC12] Lin Ma and Roger D. Chamberlain. A performance model for memory bandwidth constrained applications on graphics engines. In Proc. 23rd IEEE Int'l Conf. on Application-specific Systems, Architectures and Processors, pages 24--31, July 2012. [ bib | DOI | pdf ]
[BALC12] Jeremy D. Buhler, Kunal Agrawal, Peng Li, and Roger D. Chamberlain. Efficient deadlock avoidance for streaming computation with filtering. In Proc. 17th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, pages 235--246, February 2012. [ bib | DOI | pdf ]
[LWBC11] Joseph M. Lancaster, Joseph G. Wingbermuehle, Jonathan C. Beard, and Roger D. Chamberlain. Crossing boundaries in TimeTrial: Monitoring communications across architecturally diverse computing platforms. In Proc. 9th IEEE/IFIP Int'l Conf. Embedded and Ubiquitous Computing, October 2011. [ bib | DOI | pdf ]
[LSBC11] Joseph M. Lancaster, E. F. Berkley Shands, Jeremy D. Buhler, and Roger D. Chamberlain. TimeTrial: A low-impact performance profiler for streaming data applications. In Proc. IEEE Int'l Conf. on Application-specific Systems, Architectures and Processors, September 2011. [ bib | DOI | pdf ]
[LWC11] Joseph M. Lancaster, Joseph G. Wingbermuehle, and Roger D. Chamberlain. Asking for performance: Exploiting developer intuition to guide instrumentation with TimeTrial. In Proc. 13th Int'l Conf. High Performance Computing and Communications, September 2011. [ bib | DOI | pdf ]
[PCC11] Shobana Padmanabhan, Yixin Chen, and Roger D. Chamberlain. Optimal design-space exploration of streaming applications. In Proc. IEEE Int'l Conf. Application-specific Systems, Architectures and Processors, pages 227--230, September 2011. [ bib | DOI | pdf ]
[MCBF11] Lin Ma, Roger D. Chamberlain, Jeremy D. Buhler, and Mark A. Franklin. Bloom filter performance on graphics engines. In Proc. of 40th International Conference on Parallel Processing, pages 522--531, September 2011. [ bib | DOI | pdf ]
[Lan11] Joseph M. Lancaster. Low-Impact Profiling of Streaming, Hetergeneous Applications. PhD thesis, Dept. of Computer Science and Engineering, Washington University in St. Louis, August 2011. [ bib ]
[HGC11] Michael J. Hall, Viktor Gruev, and Roger D. Chamberlain. Noise analysis of a current-mode read circuit for sensing magnetic tunnel junction resistance. In Proc. of IEEE International Symposium on Circuits and Systems, pages 1816--1819, May 2011. [ bib | DOI | pdf ]
[LC10] Joseph M. Lancaster and Roger D. Chamberlain. Crossing timezones in the TimeTrial performance monitor. In Proc. Symposium on Application Accelerators in High Performance Computing, July 2010. [ bib | pdf ]
[PCC10] Shobana Padmanabhan, Yixin Chen, and Roger D. Chamberlain. Design-space optimization for automatic acceleration of streaming applications. In Proc. Symposium on Application Accelerators in High Performance Computing, July 2010. [ bib | DOI | pdf ]
[LAB+10] Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain, and Joseph M. Lancaster. Deadlock-avoidance for streaming applications with split-join structure: Two case studies. In Proc. 21st IEEE Int'l Conf. Application-specific Systems, Architectures and Processors, pages 333--336, July 2010. [ bib | DOI | pdf ]
[DLF+10] Rahav Dor, Joseph M. Lancaster, Mark A. Franklin, Jeremy Buhler, and Roger D. Chamberlain. Using queuing theory to model streaming applications. In Proc. of 2010 Symposium on Application Accelerators in High Performance Computing, July 2010. [ bib ]
[LABC10] Peng Li, Kunal Agrawal, Jeremy Buhler, and Roger D. Chamberlain. Deadlock avoidance for streaming computation with filtering. In Proc. 22nd ACM Symposium on Parallelism in Algorithms and Architectures, pages 243--252, June 2010. [ bib | pdf ]
[CFT+10] Roger D. Chamberlain, Mark A. Franklin, Eric J. Tyson, James H. Buckley, Jeremy Buhler, Greg Galloway, Saurabh Gayen, Michael Hall, E.F. Berkley Shands, and Naveen Singla. Auto-Pipe: Streaming applications on architecturally diverse systems. Computer, 43(3):42--49, March 2010. [ bib | DOI ]
[CBFB10] Roger D. Chamberlain, Jeremy Buhler, Mark Franklin, and James H. Buckley. Application-guided tool development for architecturally diverse computation. In Proc. Symp. on Applied Computing, pages 496--501, March 2010. [ bib | DOI | pdf ]
[JBC10a] A. Jacob, J. Buhler, and R. Chamberlain. Design of throughput-optimized arrays from recurrence abstractions. In Proc. of 21st IEEE Int'l Conf. Application-specific Systems, Architectures and Processors, pages 133--40, 2010. [ bib ]
[JBC10b] A. Jacob, J. Buhler, and R. Chamberlain. Rapid RNA folding: Analysis and acceleration of the Zuker recurrence. In Proc. of 18th IEEE Int'l Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 87--94, 2010. [ bib ]
[Jac10] A. Jacob. Parallelization of Dynamic Programming Recurrences in Computational Biology. PhD thesis, washington University, St. Louis, MO, 2010. [ bib ]
[LBC09b] Joseph M. Lancaster, Jeremy D. Buhler, and Roger D. Chamberlain. Efficient runtime performance monitoring of FPGA-based applications. In Proc. 22nd IEEE Int'l System-on-Chip Conf., pages 23--28, September 2009. [ bib | DOI | pdf ]
[LBC09a] J. Lancaster, J. Buhler, and R. D. Chamberlain. Acceleration of ungapped extension in Mercury BLAST. Journal of Microprocessors and Microsystems, 33(4):281--289, June 2009. [ bib | DOI ]
[SHSC08] Naveen Singla, Michael Hall, Berkley Shands, and Roger D. Chamberlain. Financial Monte Carlo simulation on architecturally diverse systems. In Proc. Workshop on High Performance Computational Finance, November 2008. [ bib | DOI | pdf ]
[BC08] Michela Becchi and Patrick Crowley. Efficient regular expression evaluation: Theory to practice. In Proc. ACM/IEEE Symp. on Architectures for Networking and Communications Systems, pages 50--59, November 2008. [ bib | DOI ]
[TBFC08] Eric J. Tyson, James Buckley, Mark A. Franklin, and Roger D. Chamberlain. Acceleration of atmospheric Cherenkov telescope signal processing to real-time speed with the Auto-Pipe design system. Nuclear Inst. and Methods in Physics Research A, 585(2):474--479, October 2008. [ bib | DOI ]
[BFC08] Michela Becchi, Mark A. Franklin, and Patrick Crowley. A workload for evaluating deep packet inspection architectures. In Proc. IEEE Int'l Symp. on Workload Characterization, pages 79--89, September 2008. [ bib | DOI ]
[Bed08] Justin Bedings. Software and Hardware Acceleration of the Genomic Motif Finding Tool PhyloNet. Master's thesis, Dept. of Computer Science and Engineering, Washington University in St. Louis, August 2008. [ bib | pdf ]
[JLB+08] Arpith Jacob, Joseph Lancaster, Jeremy Buhler, Brandon Harris, and Roger D. Chamberlain. Mercury BLASTP: Accelerating protein sequence alignment. ACM Trans. Reconfigurable Technol. Syst., 1(2):1--44, June 2008. [ bib | DOI ]
[Gay08] Saurabh Gayen. X-Sim and X-Eval: Tools for simulation and analysis of heterogeneous pipelined architectures. Master's thesis, Dept. of Computer Science and Engineering, Washington University in St. Louis, May 2008. [ bib | pdf ]
[CLC08] Roger D. Chamberlain, Joseph Lancaster, and Ron Cytron. Visions for application development on hybrid computing systems. Parallel Computing, 34(4--5):201--216, May 2008. [ bib | DOI ]
[GFTC08] Saurabh Gayen, Mark A. Franklin, Eric J. Tyson, and Roger D. Chamberlain. Simulation of streaming applications on multicore systems. In Proc. 3rd Workshop on Software Tools for MultiCore Systems, April 2008. [ bib | pdf ]
[KC08] Praveen Krishnamurthy and Roger D. Chamberlain. Analytic performance models for bounded queueing systems. In Proc. Workshop on Advances of Parallel and Distributed Computing Models, April 2008. [ bib | pdf ]
[LCC08] Joseph Lancaster, Ron Cytron, and Roger D. Chamberlain. Understanding the performance of streaming applications deployed on hybrid systems. In Proc. Next Generation Software Workshop, April 2008. [ bib | DOI | pdf ]
[BC07] Michela Becchi and Patrick Crowley. An improved algorithm to accelerate regular expression evaluation. In Proc. ACM/IEEE Symp. on Architectures for Networking and Communications Systems, pages 145--154, December 2007. [ bib | DOI ]
[CTG+07] Roger D. Chamberlain, Eric J. Tyson, Saurabh Gayen, Mark A. Franklin, Jeremy Buhler, Patrick Crowley, and James Buckley. Application development on hybrid systems. In Proc. ACM/IEEE Conf. on Supercomputing, November 2007. [ bib | DOI | pdf ]
[KBC+07] Praveen Krishnamurthy, Jeremy Buhler, Roger Chamberlain, Mark Franklin, Kwame Gyang, Arpith Jacob, and Joseph Lancaster. Biosequence similarity search on the Mercury system. Journal of VLSI Signal Processing, 49(1):101--121, October 2007. [ bib | DOI ]
[CF07] Roger D. Chamberlain and Mark A. Franklin. Automatic deployment of streaming applications on hybrid architectures. In Proc. 11th High Performance Embedded Computing Workshop, September 2007. [ bib | pdf ]
[CS07b] Roger D. Chamberlain and Berkley Shands. Performance of direct attached disk subsystems. In Proc. 11th High Performance Embedded Computing Workshop, September 2007. [ bib | pdf ]
[CS07a] Roger D. Chamberlain and Berkley Shands. Direct-attached disk subsystem performance assessment. In Proc. 4th Int'l Workshop on Storage Network Architecture and Parallel I/Os, September 2007. [ bib | pdf ]
[HJL+07] Brandon Harris, Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, and Roger D. Chamberlain. A banded Smith-Waterman FPGA accelerator for Mercury BLASTP. In Proc. 17th Int'l Conf. on Field Programmable Logic and Applications (FPL), August 2007. [ bib | DOI | pdf ]
[BLJC07] Jeremy D. Buhler, Joseph M. Lancaster, Arpith C. Jacob, and Roger D. Chamberlain. Mercury BLASTN: Faster DNA sequence comparison using a streaming hardware architecture. In Proc. Reconfigurable Systems Summer Institute, July 2007. [ bib | pdf ]
[GTFC07] Saurabh Gayen, Eric J. Tyson, Mark A. Franklin, and Roger D. Chamberlain. A federated simulation environment for hybrid systems. In Proc. 21st Int'l Workshop on Principles of Advanced and Distributed Simulation, June 2007. [ bib | pdf ]
[BFC07] Michela Becchi, Mark A. Franklin, and Patrick Crowley. Performance/area efficiency in chip multiprocessors with micro-caches. In Proc. ACM Int'l Conf. on Computing Frontiers, pages 247--258, May 2007. [ bib | DOI ]
[JLBC07b] Arpith Jacob, Joseph Lancaster, Jeremy Buhler, and Roger D. Chamberlain. FPGA-accelerated seed generation in Mercury BLASTP. In Proc. 15th IEEE Symposium on Field-Programmable Custom Computing Machines, April 2007. [ bib | DOI | pdf ]
[JLBC07a] A. Jacob, J. Lancaster, J. Buhler, and R. Chamberlain. Preliminary results in accelerating profile HMM search on FPGAs. In Proc. 6th IEEE Int'l Workshop on High Performance Computational Biology, March 2007. [ bib ]
[BLJ+07] Jeremy D Buhler, Joseph M Lancaster, Arpith C Jacob, Roger D Chamberlain, et al. Mercury blastn: Faster dna sequence comparison using a streaming hardware architecture. Proc. of Reconfigurable Systems Summer Institute, 2007. [ bib | pdf ]
[Kri06] Praveen Krishnamurthy. Performance Evaluation for Hybrid Architectures. PhD thesis, Dept. of Computer Science and Engineering, Washington University in St. Louis, December 2006. [ bib | pdf ]
[CFBC06] Patrick Crowley, Mark A. Franklin, Jeremy Buhler, and Roger D. Chamberlain. Impact of CMP design on high-performance embedded computing. In Proc. 10th High Performance Embedded Computing Workshop, September 2006. [ bib | pdf ]
[CFI06] Roger D. Chamberlain, Mark A. Franklin, and Ronald S. Indeck. Exploiting reconfigurability for text search. In Proc. 10th High Performance Embedded Computing Workshop, September 2006. [ bib | pdf ]
[GTF+06] Saurabh Gayen, Eric J. Tyson, Mark A. Franklin, Roger D. Chamberlain, and Patrick Crowley. X-Sim: A federated heterogeneous simulation environment. In Proc. 10th High Performance Embedded Computing Workshop, September 2006. [ bib | pdf ]
[Tys06] Eric J. Tyson. Auto-Pipe and the X language: A toolset and language for the simulation, analysis, and synthesis of heterogeneous pipelined architectures. Master's thesis, Dept. of Computer Science and Engineering, Washington University in St. Louis, August 2006. [ bib | pdf ]
[MBC+06] Rahul P. Maddimsetty, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, and Brandon Harris. Accelerator design for protein sequence HMM search. In Proc. 20th ACM Int'l Conf. on Supercomputing, June 2006. [ bib | DOI | pdf ]
[BC06] Michela Becchi and Patrick Crowley. Dynamic thread assignment on heterogeneous multiprocessor architectures. In Proc. ACM Int'l Conf. on Computing Frontiers, pages 29--40, May 2006. [ bib | DOI ]
[Mad06] Rahul P. Maddimsetty. Acceleration of profile-HMM search for protein sequences in reconfigurable hardware. Master's thesis, Dept. of Computer Science and Engineering, Washington University in St. Louis, May 2006. [ bib | pdf ]
[FTB+06] Mark A. Franklin, Eric J. Tyson, James Buckley, Patrick Crowley, and John Maschmeyer. Auto-pipe and the X language: A pipeline design tool and description language. In Proc. Int'l Parallel and Distributed Processing Symp., April 2006. [ bib | DOI | pdf ]
[SC06] Gary Stiehr and Roger D. Chamberlain. Improving cluster utilization through intelligent processor sharing. In Proc. 2nd Workshop on System Management Tools for Large-Scale Parallel Systems, April 2006. [ bib | pdf ]
[CS05] Roger D. Chamberlain and Berkley Shands. Streaming data from disk store to application. In Proc. 3rd Int'l Workshop on Storage Network Architecture and Parallel I/Os, pages 17--23, September 2005. [ bib | pdf ]
[FCC+05] Mark A. Franklin, Patrick Crowley, Roger D. Chamberlain, Jeremy Buhler, and James H. Buckley. Application development for hybrid pipelined systems. In Proc. 9th High Performance Embedded Computing Workshop, September 2005. [ bib | pdf ]
[CSW04] Roger Chamberlain, Berkley Shands, and Jason White. Achieving real data throughput for an FPGA co-processor on commodity server platforms. In Proc. 1st Workshop on Building Block Engine Architectures for Computers and Networks, October 2004. [ bib | pdf ]
[FCH+04] Mark A. Franklin, Roger D. Chamberlain, Michael Henrichs, Berkley Shands, and Jason White. An architecture for fast processing of large unstructured data sets. In Proc. IEEE 22nd Int'l Conf. on Computer Design, pages 280--287, October 2004. [ bib | DOI | pdf ]
[KBC+04] Praveen Krishnamurthy, Jeremy Buhler, Roger Chamberlain, Mark Franklin, Kwame Gyang, and Joseph Lancaster. Biosequence similarity search on the Mercury system. In Proc. the IEEE 15th Int'l Conf. on Application-Specific Systems, Architectures and Processors, pages 365--375, September 2004. [ bib | pdf ]
[DCE+02] Michael D. DeVore, Roger D. Chamberlain, George L. Engel, Joseph A. O'Sullivan, and Mark A. Franklin. Tradeoffs between quality of results and resource consumption in a recognition system. In Proc. of IEEE Int'l Conf. on Application-specific Systems, Architectures and Processors, pages 391--402, July 2002. [ bib ]
[NC99] Bradley L. Noble and Roger D. Chamberlain. Performance model for speculative simulation using predictive optimism. In Proc. of Hawaii International Conference on System Sciences, volume 8, January 1999. [ bib | DOI | pdf ]
[CF93] Roger D. Chamberlain and Mark A. Franklin. Performance effects of synchronization in parallel processors. In Proc. of 5th Symp. on Parallel and Distributed Processing, pages 611--616, December 1993. [ bib ]